The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2012

Filed:

Oct. 07, 2010
Applicants:

Kazuhiko Yamaguchi, Isehara, JP;

Kazuhiro Fujinuma, Ebina, JP;

Inventors:

Kazuhiko Yamaguchi, Isehara, JP;

Kazuhiro Fujinuma, Ebina, JP;

Assignee:

Anritsu Corporation, Atsugi-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization meansfor synchronizing a data output unitwith a multiplexerhas a phase comparatorfor comparing the phase of a data synchronization clock signal outputted from a data output unitin synchronization with the timing to update parallel data, with the phase of a divided clock signal A produced by dividing the frequency of a reference clock signal CKby a plural number 'm' in the multiplexer, the signal A being used for determining the timing to performing parallel-serial conversion, a variable delay devicefor adding a desired delay to a data request signal A', the variable delay devicebeing constituted by an orthogonal modulation type delay device, and a control unitfor controlling a direct control signal to be inputted into the variable delay deviceon the basis of a comparing result obtained from the phase comparatorto synchronize the timing to have the data output unitupdate the parallel data with the timing to have the multiplexerperform parallel-serial conversion processing.


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