The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2012

Filed:

May. 10, 2010
Applicants:

Jingjing Chen, Beijing, CN;

Ganming Qin, Chandler, AZ (US);

Edouard D. DE Fresart, Tempe, AZ (US);

Pon Sung Ku, Gilbert, AZ (US);

Inventors:

Jingjing Chen, Beijing, CN;

Ganming Qin, Chandler, AZ (US);

Edouard D. de Fresart, Tempe, AZ (US);

Pon Sung Ku, Gilbert, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.


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