The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Feb. 22, 2007
Jason R. Baumgartner, Austin, TX (US);
Ali S. El-zein, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
Fadi A. Zaraket, Austin, TX (US);
Jason R. Baumgartner, Austin, TX (US);
Ali S. El-Zein, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
Fadi A. Zaraket, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.