Techniques for controlling a direct injection semiconductor memory device

Abstract

Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line and applying a second voltage potential to a second region of the memory device via a source line. The method may also comprise applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, wherein the body region is electrically floating and disposed between the first region and the second region. The method may further comprise applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.