The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Apr. 27, 2011
Applicants:
Kazuo Tanaka, Tokyo, JP;
Hiroyuki Mizuno, Tokyo, JP;
Rie Nishiyama, Tokyo, JP;
Manabu Miyamoto, Tokyo, JP;
Inventors:
Kazuo Tanaka, Tokyo, JP;
Hiroyuki Mizuno, Tokyo, JP;
Rie Nishiyama, Tokyo, JP;
Manabu Miyamoto, Tokyo, JP;
Assignees:
Renesas Electronics Corporation, Kanagawa, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/20 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
Abstract
In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.