The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Feb. 08, 2008
Jong Hoon OH, Chapel Hill, NC (US);
Klaus Hummler, Apex, NC (US);
Oliver Kiehl, Charlotte, VT (US);
Josef Schnell, Charlotte, VT (US);
Wayne Frederick Ellis, Jericho, VT (US);
Jung Pil Kim, Cary, NC (US);
Lee Ward Collins, Cary, NC (US);
Octavian Beldiman, South Burlington, VT (US);
Jong Hoon Oh, Chapel Hill, NC (US);
Klaus Hummler, Apex, NC (US);
Oliver Kiehl, Charlotte, VT (US);
Josef Schnell, Charlotte, VT (US);
Wayne Frederick Ellis, Jericho, VT (US);
Jung Pil Kim, Cary, NC (US);
Lee Ward Collins, Cary, NC (US);
Octavian Beldiman, South Burlington, VT (US);
Qimonda AG, Munich, DE;
Abstract
A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.