The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Jun. 11, 2009
Won-je Park, Yongin-si, KR;
Young-hoon Park, Suwon-si, KR;
Ui-sik Kim, Seongnam-si, KR;
Dae-cheol Seong, Seoul, KR;
Yeo-ju Yoon, Uijeongbu-si, KR;
Bo-bae Keang, Yongin-si, KR;
Won-Je Park, Yongin-si, KR;
Young-Hoon Park, Suwon-si, KR;
Ui-Sik Kim, Seongnam-si, KR;
Dae-Cheol Seong, Seoul, KR;
Yeo-Ju Yoon, Uijeongbu-si, KR;
Bo-Bae Keang, Yongin-si, KR;
Samsung Electronics Co., Ltd., Su-Won Si, KR;
Abstract
In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep Ptype well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.