The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Nov. 01, 2006
Alexander Kotov, Sunnyvale, CA (US);
Amitay Levi, Cupertino, CA (US);
Hung Q. Nguyen, Fremont, CA (US);
Pavel Klinger, San Jose, CA (US);
Alexander Kotov, Sunnyvale, CA (US);
Amitay Levi, Cupertino, CA (US);
Hung Q. Nguyen, Fremont, CA (US);
Pavel Klinger, San Jose, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.