The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Dec. 30, 2008
Kee-jeung Lee, Icheon-si, KR;
Jae-sung Roh, Icheon-si, KR;
Deok-sin Kil, Icheon-si, KR;
Young-dae Kim, Icheon-si, KR;
Jin-hyock Kim, Icheon-si, KR;
Kwan-woo DO, Icheon-si, KR;
Kyung-woong Park, Icheon-si, KR;
Jeong-yeop Lee, Icheon-si, KR;
Kee-Jeung Lee, Icheon-si, KR;
Jae-Sung Roh, Icheon-si, KR;
Deok-Sin Kil, Icheon-si, KR;
Young-Dae Kim, Icheon-si, KR;
Jin-Hyock Kim, Icheon-si, KR;
Kwan-Woo Do, Icheon-si, KR;
Kyung-Woong Park, Icheon-si, KR;
Jeong-Yeop Lee, Icheon-si, KR;
Hynix Semiconductor Inc., Icheon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.