The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Sep. 18, 2009
Yezdi Dordi, Palo Alto, CA (US);
John Boyd, Hillsboro, OR (US);
Fritz Redeker, Fremont, CA (US);
William Thie, Mountain View, CA (US);
Tiruchirapalli Arunagiri, Fremont, CA (US);
Alex Yoon, San Jose, CA (US);
Yezdi Dordi, Palo Alto, CA (US);
John Boyd, Hillsboro, OR (US);
Fritz Redeker, Fremont, CA (US);
William Thie, Mountain View, CA (US);
Tiruchirapalli Arunagiri, Fremont, CA (US);
Alex Yoon, San Jose, CA (US);
Lam Research Corporation, Fremont, CA (US);
Abstract
This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.