The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2012

Filed:

May. 29, 2009
Applicants:

Kazuya Ohkawa, Tokyo, JP;

Shinya Jyumonji, Tokyo, JP;

Masumi Taninaka, Tokyo, JP;

Hiroshi Hamano, Tokyo, JP;

Masumi Koizumi, Tokyo, JP;

Inventors:

Kazuya Ohkawa, Tokyo, JP;

Shinya Jyumonji, Tokyo, JP;

Masumi Taninaka, Tokyo, JP;

Hiroshi Hamano, Tokyo, JP;

Masumi Koizumi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B41J 2/45 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A composite semiconductor device is formed of a semiconductor wafer having a plurality of device-forming areas in which semiconductor elements are formed and dicing areas defined between the device-forming areas, and is formed by dicing the semiconductor wafer at the dicing areas. The composite semiconductor device includes a semiconductor substrate, and a plurality of wiring layers layered on the semiconductor substrate. The wiring layers include at least conductive films. Connecting portions are formed to connect the wiring layers with each other in a layering direction of the wiring layers. Each of the connecting portions is disposed on the device-forming area side with respect to a dicing position defined in the dicing area.


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