The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Oct. 31, 2009
Pankaj Kumar, Karnataka, IN;
Pramod Elamannu Parameswaran, Karnataka, IN;
Makeshwar Kothandaraman, Whitehall, PA (US);
Vani Deshpande, Karnataka, IN;
John Kriz, Palmerton, PA (US);
Pankaj Kumar, Karnataka, IN;
Pramod Elamannu Parameswaran, Karnataka, IN;
Makeshwar Kothandaraman, Whitehall, PA (US);
Vani Deshpande, Karnataka, IN;
John Kriz, Palmerton, PA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.