The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2012

Filed:

Oct. 29, 2008
Applicants:

Hien Phu Dang, Nanuet, NY (US);

Vijayeshwar Das Khanna, Millwood, NY (US);

Arun Sharma, New Rochelle, NY (US);

Sri M. Sri-jayantha, Ossining, NY (US);

Inventors:

Hien Phu Dang, Nanuet, NY (US);

Vijayeshwar Das Khanna, Millwood, NY (US);

Arun Sharma, New Rochelle, NY (US);

Sri M. Sri-Jayantha, Ossining, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of characterizing an organic substrate including a plurality of circuit layers is provided includes the steps of: receiving an image of the organic substrate, the image including a geometric description of the circuit layers of the substrate; segmenting the substrate into multiple processing regions based, at least in part, on geometric coordinates of circuit structures defined in the image of the substrate; generating a circuit layer image corresponding to a selected one of the processing regions of the substrate; identifying one or more geometric features in the circuit layer image; estimating at least one thermomechanical property of the circuit layer image as a function of the identified geometric features; repeating the steps of receiving an image, generating a circuit layer image, identifying one or more geometric features in the circuit layer image, and estimating at least one thermomechanical property of the circuit layer image until all circuit layers in the substrate have been processed; and generating a 3-D representation of the selected one of the processing regions of the substrate including the plurality of circuit layer images as a function of the at least one thermomechanical property of each of the plurality of circuit layer images.


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