The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2012
Filed:
Dec. 31, 2008
Lihu Rappoport, Haifa, IL;
Chen Koren, Haifa, IL;
Franck Sala, Haifa, IL;
Oded Lempel, Amikam, IL;
Ido Ouziel, Haifa, IL;
Ilhyun Kim, Beaverton, OR (US);
Ron Gabor, Raanana, IL;
Lior Libis, Haifa, IL;
Gregory Pribush, Haifa, IL;
Lihu Rappoport, Haifa, IL;
Chen Koren, Haifa, IL;
Franck Sala, Haifa, IL;
Oded Lempel, Amikam, IL;
Ido Ouziel, Haifa, IL;
Ilhyun Kim, Beaverton, OR (US);
Ron Gabor, Raanana, IL;
Lior Libis, Haifa, IL;
Gregory Pribush, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.