The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2012
Filed:
Oct. 22, 2007
Shuhichi Okabe, Gyunggi-Do, KR;
Myung-sam Kang, Suwon-si, KR;
Jung-hyun Park, Suwon-si, KR;
Hoe-ku Jung, Daejeon, KR;
Jeong-woo Park, Suwon-si, KR;
Ji-eun Kim, Gwangmyeong-si, KR;
Shuhichi Okabe, Gyunggi-Do, KR;
Myung-Sam Kang, Suwon-si, KR;
Jung-Hyun Park, Suwon-si, KR;
Hoe-Ku Jung, Daejeon, KR;
Jeong-Woo Park, Suwon-si, KR;
Ji-Eun Kim, Gwangmyeong-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.