The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8120096 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 21, 2012

Filed:

Mar. 03, 2009
Applicants:

Hong Pyo Heo, Gumi-si, KR;

Keum Hwang, Gumi-si, KR;

Inventors:

Hong Pyo Heo, Gumi-si, KR;

Keum Hwang, Gumi-si, KR;

Assignee:

KEC Corporation, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power semiconductor device includes first conductive regions, formed to a predetermined depth in a surface of a conductive low concentration epitaxial layer. The first conductive regions include linear first conductive layers spaced from each other and linear second conductive layers spaced from each other. Second conductive regions are formed to a smaller width and depth than the first and second conductive layers to form channels in the first and second conductive layers. A gate oxide layer formed on a surface of the epitaxial layer defines first windows having a smaller width than the first conductive layers and second windows having a smaller width than the second conductive layers. A gate polysilicon layer is formed on the gate oxide layer.


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