The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2012

Filed:

May. 28, 2008
Applicants:

Suk-kang Sung, Gyeonggi-do, KR;

Choong-ho Lee, Gyeonggi-do, KR;

Sang-wook Lim, Gyeonggi-do, KR;

Dong-uk Choi, Gyeonggi-do, KR;

Hee-soo Kang, Gyeonggi-do, KR;

Kyu-charn Park, Gyeonggi-do, KR;

Inventors:

Suk-Kang Sung, Gyeonggi-do, KR;

Choong-Ho Lee, Gyeonggi-do, KR;

Sang-wook Lim, Gyeonggi-do, KR;

Dong-Uk Choi, Gyeonggi-do, KR;

Hee-Soo Kang, Gyeonggi-do, KR;

Kyu-Charn Park, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.


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