The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Jul. 07, 2009
Kong-soo Lee, Gyeonggi-do, KR;
Kyoung-seok Kim, Seoul, KR;
Sang-jin Park, Gyeonggi-do, KR;
Chang-hoon Lee, Gyeonggi-do, KR;
Ji-hyun Jeong, Seoul, KR;
Jae-hyun Park, Gyeonggi-do, KR;
Jae-hee OH, Gyeonggi-do, KR;
Kong-Soo Lee, Gyeonggi-do, KR;
Kyoung-Seok Kim, Seoul, KR;
Sang-Jin Park, Gyeonggi-do, KR;
Chang-Hoon Lee, Gyeonggi-do, KR;
Ji-Hyun Jeong, Seoul, KR;
Jae-Hyun Park, Gyeonggi-do, KR;
Jae-Hee Oh, Gyeonggi-do, KR;
Abstract
Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.