The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Apr. 30, 2009
Anwar Ali, San Jose, CA (US);
Kalyan Doddapaneni, Milpitas, CA (US);
Gokulnath Sulur, Sunnyvale, CA (US);
Wilson Leung, San Francisco, CA (US);
Tauman T Lau, San Jose, CA (US);
Anwar Ali, San Jose, CA (US);
Kalyan Doddapaneni, Milpitas, CA (US);
Gokulnath Sulur, Sunnyvale, CA (US);
Wilson Leung, San Francisco, CA (US);
Tauman T Lau, San Jose, CA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
An integrated circuit includes a number of probe pads arranged in a staggered manner in a core region of the integrated circuit and a number of bond pads in an Input/Output (I/O) region surrounding the core region. The core region includes logic circuitry therein, and the I/O region is configured to enable the core region to communicate with one or more external circuit(s) through the number of bond pads. The integrated circuit also includes a die metal interconnect separating a bond pad area in the I/O region from a probe pad area in the core region. A dimension of the die metal interconnect and/or a position of the die metal interconnect between the probe pad area and the bond pad area is variable.