The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Sep. 25, 2007
Huilong Zhu, Poughkeepsie, NY (US);
Brian J. Greene, Wappingers Falls, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Gregory G. Freeman, Hopewell Junction, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Brian J. Greene, Wappingers Falls, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Gregory G. Freeman, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.