The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Sep. 20, 2007
Hong-suk Kim, Yongin-si, KR;
Si-young Choi, Seongnam-si, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Han-mei Choi, Seoul, KR;
Seung-hwan Lee, Suwon-si, KR;
Seung-jae Baik, Seoul, KR;
Sun-jung Kim, Suwon-si, KR;
Kwang-min Park, Seoul, KR;
In-sun Yi, Suwon-si, KR;
Hong-Suk Kim, Yongin-si, KR;
Si-Young Choi, Seongnam-si, KR;
Ki-Hyun Hwang, Seongnam-si, KR;
Han-Mei Choi, Seoul, KR;
Seung-Hwan Lee, Suwon-si, KR;
Seung-Jae Baik, Seoul, KR;
Sun-Jung Kim, Suwon-si, KR;
Kwang-Min Park, Seoul, KR;
In-Sun Yi, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.