The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Aug. 28, 2009
Weize Xiong, Plano, TX (US);
Zhiqiang Wu, Plano, TX (US);
Xin Wang, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated process flow for forming an NMOS transistor () and an embedded SiGe (eSiGe) PMOS transistor () using a stress memorization technique (SMT) layer (). The SMT layer () is deposited over both the NMOS transistor () and PMOS transistor (). The portion of SMT layer () over PMOS transistor () is anisotropically etched to form spacers () without etching the portion of SMT layer () over NMOS transistor (). Spacers () are used to align the SiGe recess etch and growth to form SiGe source/drain regions (). The source/drain anneals are performed after etching the SMT layer () such that SMT layer () provides the desired stress to the NMOS transistor () without degrading PMOS transistor ().