The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8114686 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2012

Filed:

Jun. 21, 2010
Applicants:

Nazmul Habib, South Burlington, VT (US);

Chung Hon Lam, Peekskill, NY (US);

Robert Mcmahon, Essex Junction, VT (US);

Inventors:

Nazmul Habib, South Burlington, VT (US);

Chung Hon Lam, Peekskill, NY (US);

Robert McMahon, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 25/02 (2006.01); G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.


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