The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2012
Filed:
Nov. 24, 2008
Yinan Shen, Sunnyvale, CA (US);
Chih-chung Chen, Palo Alto, CA (US);
BO Wang, Shanghai, CN;
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit design to a plurality of components of the PLD, wherein each of the mapped PLD components is associated with one of a plurality of regions of the PLD and with one or more unique signal paths entering the PLD region. The method also includes determining a cost value for each PLD region based at least in part on the number of unique signal paths entering the PLD region from other PLD regions. The method also includes selecting one of the PLD components to move from a first one of the PLD regions to a second one of the PLD regions. The method also includes updating the cost values associated with the first and second PLD regions based on a change in the number of unique signal paths entering the first and second PLD regions. The method also includes selectively accepting or rejecting the move based at least in part on the updated cost values.