The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2012
Filed:
Oct. 13, 2009
Shyam Chandra, Portland, OR (US);
OM Agrawal, Los Altos, CA (US);
Ludmil Nikolov, Chippenham, GB;
Harald Weller, Romsey, GB;
Douglas Morse, Bath, GB;
Shyam Chandra, Portland, OR (US);
Om Agrawal, Los Altos, CA (US);
Ludmil Nikolov, Chippenham, GB;
Harald Weller, Romsey, GB;
Douglas Morse, Bath, GB;
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.