The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2012
Filed:
May. 24, 2010
Ronald P. Cocchi, Seal Beach, CA (US);
James P. Baukus, Westlake Village, CA (US);
Bryan J. Wang, S. Lake Tahoe, CA (US);
Lap Wai Chow, S. Pasadena, CA (US);
Paul Ouyang, San Jose, CA (US);
Ronald P. Cocchi, Seal Beach, CA (US);
James P. Baukus, Westlake Village, CA (US);
Bryan J. Wang, S. Lake Tahoe, CA (US);
Lap Wai Chow, S. Pasadena, CA (US);
Paul Ouyang, San Jose, CA (US);
Syphermedia International, Inc., Westminster, CA (US);
Promtek Programmable Memory Technology, Inc., San Jose, CA (US);
Abstract
A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.