The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2012
Filed:
Apr. 30, 2009
Marshall O. Cathey, Jr., Denison, TX (US);
Pushpa Mahalingam, Richardson, TX (US);
Weidong Tian, Dallas, TX (US);
David C. Guiling, Garland, FL (US);
Xinfen Chen, Plano, TX (US);
Binghua HU, Plano, TX (US);
Sopa Chevacharoenkul, Richardson, TX (US);
Marshall O. Cathey, Jr., Denison, TX (US);
Pushpa Mahalingam, Richardson, TX (US);
Weidong Tian, Dallas, TX (US);
David C. Guiling, Garland, FL (US);
Xinfen Chen, Plano, TX (US);
Binghua Hu, Plano, TX (US);
Sopa Chevacharoenkul, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.