The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2012
Filed:
Mar. 19, 2008
Donna N. Dillenberger, Yorktown Heights, NY (US);
Greg A. Dyck, Morgan Hill, CA (US);
Stephen J. Heisig, Tarrytown, NY (US);
Bernard R. Pierce, Poughkeepsie, NY (US);
Donald W. Schmidt, Stone Ridge, NY (US);
Gong Su, New York, NY (US);
Donna N. Dillenberger, Yorktown Heights, NY (US);
Greg A. Dyck, Morgan Hill, CA (US);
Stephen J. Heisig, Tarrytown, NY (US);
Bernard R. Pierce, Poughkeepsie, NY (US);
Donald W. Schmidt, Stone Ridge, NY (US);
Gong Su, New York, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A computer-implemented method for distributing a plurality of tasks over a plurality of processing nodes in a processor network includes the following steps: calculating a task process consumption value for the tasks; calculating a measured node processor consumption value for the nodes; calculating a target node processor consumption value for the nodes, the target node processor consumption value indicating optimal node processor consumption; calculating a load index value as a difference between the calculated node processor consumption value for a node i and the target node processor consumption value for node i; and distributing the tasks among the nodes to balance a processor workload among the nodes, according to the calculated load index value, such that the calculated load index value of each node is substantially zero. The method further embodies a multi-dimensional balancing matrix, each dimension of the matrix representing a node corresponding to a different processor type and each cell representing tasks assigned to multiple nodes.