The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2012
Filed:
Mar. 12, 2009
Krishnan Srinivasan, Cupertino, CA (US);
Drew E. Wingard, Palo Alto, CA (US);
Vida Vakilotojar, Mountain View, CA (US);
Chien-chun Chou, Saratoga, CA (US);
Krishnan Srinivasan, Cupertino, CA (US);
Drew E. Wingard, Palo Alto, CA (US);
Vida Vakilotojar, Mountain View, CA (US);
Chien-Chun Chou, Saratoga, CA (US);
Sonics, Inc., Milpitas, CA (US);
Abstract
Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.