The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Dec. 20, 2005
Applicants:

Hidenori Sato, Tokyo, JP;

Hiroyasu Nousou, Tokyo, JP;

Yoshitaka Fujiishi, Tokyo, JP;

Hiroaki Sekikawa, Tokyo, JP;

Inventors:

Hidenori Sato, Tokyo, JP;

Hiroyasu Nousou, Tokyo, JP;

Yoshitaka Fujiishi, Tokyo, JP;

Hiroaki Sekikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region () where DRAM cells are formed is defined by an isolation trench () formed in a silicon substrate (). The isolation trench () has an isolation insulating film () formed therein. Each DRAM cell includes a MOS transistor having a gate electrode () with sidewalls (), and a capacitor having an upper electrode () with sidewalls (). A recess () is formed in the upper portion of the isolation trench (), and the upper electrode () of the capacitor has a buried portion buried in the recess (). The outer edge (E) of the buried portion of the upper electrode () is located inside the outer edge (E) of the sidewalls ().


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