Processor for executing an aes-type algorithm

Abstract

A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register () containing an input data block column; an output register () containing an output data block column or an intermediate block column; a second input register () containing a key block column or the intermediate data blocks; a block substitution element () receiving the data one block at a time following the selection () thereof in the first register and providing, for each block, a column of blocks; an element () applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element () combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.