The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Sep. 12, 2003
John D. Hyde, Corvalis, OR (US);
Miguel E. Figueroa, Seattle, WA (US);
Todd E. Humes, Shoreline, WA (US);
Christopher J. Diorio, Shoreline, WA (US);
Terry D. Hass, Ballwin, MO (US);
Chad A. Lindhorst, Seattle, WA (US);
John D. Hyde, Corvalis, OR (US);
Miguel E. Figueroa, Seattle, WA (US);
Todd E. Humes, Shoreline, WA (US);
Christopher J. Diorio, Shoreline, WA (US);
Terry D. Hass, Ballwin, MO (US);
Chad A. Lindhorst, Seattle, WA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.