The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
May. 02, 2011
Takako Funakoshi, Tokyo, JP;
Eiichi Murakami, Saitama, JP;
Kazumasa Yanagisawa, Tokyo, JP;
Kan Takeuchi, Tokyo, JP;
Hideo Aoki, Tokyo, JP;
Hizuru Yamaguchi, Tokyo, JP;
Takayuki Oshima, Tokyo, JP;
Kazuyuki Tsunokuni, Iharaki, JP;
Kousuke Okuyama, Saitama, JP;
Takako Funakoshi, Tokyo, JP;
Eiichi Murakami, Saitama, JP;
Kazumasa Yanagisawa, Tokyo, JP;
Kan Takeuchi, Tokyo, JP;
Hideo Aoki, Tokyo, JP;
Hizuru Yamaguchi, Tokyo, JP;
Takayuki Oshima, Tokyo, JP;
Kazuyuki Tsunokuni, Iharaki, JP;
Kousuke Okuyama, Saitama, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.