The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2012

Filed:

Oct. 18, 2010
Applicants:

Rey H. Bruce, San Jose, CA (US);

Ricardo H. Bruce, Union City, CA (US);

Patrick Digamon Bugayong, Mandaluyong City, PH;

Joel Alonzo Baylon, Cavite, PH;

Inventors:

Rey H. Bruce, San Jose, CA (US);

Ricardo H. Bruce, Union City, CA (US);

Patrick Digamon Bugayong, Mandaluyong City, PH;

Joel Alonzo Baylon, Cavite, PH;

Assignee:

BiTMICRO Networks, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01); H01L 21/66 (2006.01); H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.


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