The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8093099 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 10, 2012

Filed:

Apr. 20, 2010
Applicants:

Sampath Purushothaman, Armonk, NY (US);

Mary E. Rothwell, Armonk, CT (US);

Ghavam Ghavami Shahidi, Armonk, NY (US);

Roy Rongqing Yu, Armonk, NY (US);

Inventors:

Sampath Purushothaman, Armonk, NY (US);

Mary E. Rothwell, Armonk, CT (US);

Ghavam Ghavami Shahidi, Armonk, NY (US);

Roy Rongqing Yu, Armonk, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
Abstract

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.


Find Patent Forward Citations

Purushothaman, Sampath. (2012). Lock and key through-via method for wafer level 3d integration and structures produced (U.S. Patent No. 8093099). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8093099

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