The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2012

Filed:

Aug. 13, 2009
Applicants:

Tsung-yung (Jonathan) Chang, Cupertino, CA (US);

Durgesh Srivastava, Santa Clara, CA (US);

Jonathan Shoemaker, Sunnyvale, CA (US);

John Benoit, Sunnyvale, CA (US);

Inventors:

Tsung-Yung (Jonathan) Chang, Cupertino, CA (US);

Durgesh Srivastava, Santa Clara, CA (US);

Jonathan Shoemaker, Sunnyvale, CA (US);

John Benoit, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.


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