Method for manufacturing capacitor lower electrodes of semiconductor memory

Abstract

A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.