The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2012
Filed:
Nov. 05, 2008
Jeffrey F. Denatale, Thousand Oaks, CA (US);
Philip A. Stupar, Oxnard, CA (US);
Alexandros P. Papavasiliou, Thousand Oaks, CA (US);
Robert L. Borwick, Iii, Thousand Oaks, CA (US);
Jeffrey F. DeNatale, Thousand Oaks, CA (US);
Philip A. Stupar, Oxnard, CA (US);
Alexandros P. Papavasiliou, Thousand Oaks, CA (US);
Robert L. Borwick, III, Thousand Oaks, CA (US);
Teledyne Scientific & Imaging, LLC, Thousand Oaks, CA (US);
Abstract
A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.