The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2011

Filed:

May. 12, 2008
Applicants:

Katsuhiko Tanno, Gifu, JP;

Youichirou Kawamura, Gifu, JP;

Inventors:

Katsuhiko Tanno, Gifu, JP;

Youichirou Kawamura, Gifu, JP;

Assignee:

IBIDEN Co., Ltd., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K 31/02 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a printed wiring board having at least one solder bump includes forming a solder resist layer on a conductor layer. The solder resist layer has at least one opening that exposes a connection pad of the conductor layer, and the at least one opening in the solder resist layer has a depth D, from the solder resist layer to the exposed connection pad, of from 3 μm to 18 μm. The method also includes loading a solder ball into each of the at least one opening in the solder resist layer, and forming a bump on the exposed connection pad by heating the solder ball to a reflow temperature.


Find Patent Forward Citations

Tanno, Katsuhiko. (2011). Method for manufacturing a printed wiring board (U.S. Patent No. 8083123). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8083123

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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