The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2011

Filed:

Aug. 01, 2008
Applicants:

Andrew Benson Maki, Rochester, MN (US);

Gerald Keith Bartley, Rochester, MN (US);

Philip Raymond Germann, Oronoco, MN (US);

Mark Owen Maxson, Mantorville, MN (US);

Darryl John Becker, Rochester, MN (US);

Paul Eric Dahlen, Rochester, MN (US);

John Edward Sheets, Ii, Zumbrota, MN (US);

Inventors:

Andrew Benson Maki, Rochester, MN (US);

Gerald Keith Bartley, Rochester, MN (US);

Philip Raymond Germann, Oronoco, MN (US);

Mark Owen Maxson, Mantorville, MN (US);

Darryl John Becker, Rochester, MN (US);

Paul Eric Dahlen, Rochester, MN (US);

John Edward Sheets, II, Zumbrota, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 7/127 (2006.01); B05D 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.


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