The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2011

Filed:

Sep. 30, 2008
Applicants:

Ya-chieh Lai, Sunnyvale, CA (US);

Frank E. Gennari, San Jose, CA (US);

Matthew W Moskewicz, San Mateo, CA (US);

Junjiang Lei, San Jose, CA (US);

Weinong Lai, Fremont, CA (US);

Inventors:

Ya-Chieh Lai, Sunnyvale, CA (US);

Frank E. Gennari, San Jose, CA (US);

Matthew W Moskewicz, San Mateo, CA (US);

Junjiang Lei, San Jose, CA (US);

Weinong Lai, Fremont, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.


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