Transistor structure having an active region and a dielectric platform region

Abstract

A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region () and a dielectric platform region (). A trench () is formed adjacent to a drain () of the semiconductor device to a first depth. The etch process for forming trench () etches the dielectric platform region () to a first depth. A second trench () is etched in trench () to further isolate areas in the active region (). The etch process for forming the second trench () etches the dielectric platform region () to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (), and the second trench () is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.