The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2011
Filed:
Jun. 30, 2009
Tsvika Kurts, Haifa, IL;
Guillermo Savransky, Zichron Yakov, IL;
Jason Ratner, Kfar Yonah, IL;
Eilon Hazan, Hogla, IL;
Daniel Skaba, Tel Aviv, IL;
Sharon Elmosnino, Pardessia, IL;
Geeyarpuram N. Santhanakrishnan, Portland, OR (US);
Tsvika Kurts, Haifa, IL;
Guillermo Savransky, Zichron Yakov, IL;
Jason Ratner, Kfar Yonah, IL;
Eilon Hazan, Hogla, IL;
Daniel Skaba, Tel Aviv, IL;
Sharon Elmosnino, Pardessia, IL;
Geeyarpuram N. Santhanakrishnan, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.