The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2011
Filed:
Dec. 30, 2005
Wajdi K. Feghali, Boston, MA (US);
William C. Hasenplaugh, Jamaica Plain, MA (US);
Gilbert M. Wolrich, Framingham, MA (US);
Daniel R. Cutter, Maynard, MA (US);
Vinodh Gopal, Westboro, MA (US);
Gunnar Gaubatz, Worcester, MA (US);
Wajdi K. Feghali, Boston, MA (US);
William C. Hasenplaugh, Jamaica Plain, MA (US);
Gilbert M. Wolrich, Framingham, MA (US);
Daniel R. Cutter, Maynard, MA (US);
Vinodh Gopal, Westboro, MA (US);
Gunnar Gaubatz, Worcester, MA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.