The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2011
Filed:
Dec. 04, 2008
Xiaowei Ren, Phoenix, AZ (US);
Wayne R. Burger, Phoenix, AZ (US);
Colin Kerr, South Lanarkshire, GB;
Mark A. Bennett, Glasgow, GB;
Xiaowei Ren, Phoenix, AZ (US);
Wayne R. Burger, Phoenix, AZ (US);
Colin Kerr, South Lanarkshire, GB;
Mark A. Bennett, Glasgow, GB;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Electronic elements (″) having an active device region () and integrated passive device (IPD) region () on a common substrate () preferably include a composite dielectric region (″) in the IPD region underlying the IPD () to reduce electromagnetic (E-M) () coupling to the substrate (). Mechanical stress created by plain dielectric regions (') and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (″) in the composite dielectric region (″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (″) in the composite dielectric region (″). For silicon substrates (), non-single crystal silicon is suitable for the inclusions (″) and silicon oxide for the dielectric material (″). The inclusions (″) preferably have a blade-like shape separated by and enclosed within the dielectric material (″).