The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2011

Filed:

Feb. 18, 2010
Applicants:

Toshiaki Mori, Shinjuku-ku, JP;

Kazunori Nakamura, Shinjuku-ku, JP;

Satoru Kuramochi, Shinjuku-ku, JP;

Miyuki Akazawa, Shinjuku-ku, JP;

Koichi Nakayama, Shinjuku-ku, JP;

Inventors:

Toshiaki Mori, Shinjuku-ku, JP;

Kazunori Nakamura, Shinjuku-ku, JP;

Satoru Kuramochi, Shinjuku-ku, JP;

Miyuki Akazawa, Shinjuku-ku, JP;

Koichi Nakayama, Shinjuku-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A manufacturing method of a multilayer wiring board that includes a core board, a wiring layer, and an electrically insulating layer that are stacked on the core board. The manufacturing method forms a plurality of through holes in a core member, a thermal expansion coefficient of the core board being between 2 to 20 ppm, and the core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal. The through holes are made conductive by a conductive material, to electrically connect between the front and the back of the core board. A wiring layer and an electrically insulating layer are stacked on one surface of the core board to form a multilayer wiring layer. A capacitor is formed on the other surface of the core board.


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