The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2011
Filed:
Nov. 03, 2008
Yun-jin OH, Daejeon, KR;
Chang-hoon Han, Chungcheongnam-do, KR;
Kwang-ryul Lee, Gyeonggi-do, KR;
Hyoung-suk Kim, Chungcheongnam-do, KR;
Yun-Jin Oh, Daejeon, KR;
Chang-Hoon Han, Chungcheongnam-do, KR;
Kwang-Ryul Lee, Gyeonggi-do, KR;
Hyoung-Suk Kim, Chungcheongnam-do, KR;
Samsung Electronics Co., Ltd., Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist.