The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Dec. 23, 2008
James Andrew Garrard Seawright, Mountain View, CA (US);
Jeremy Rutledge Levitt, San Jose, CA (US);
Christophe Gauthron, Mountain View, CA (US);
James Andrew Garrard Seawright, Mountain View, CA (US);
Jeremy Rutledge Levitt, San Jose, CA (US);
Christophe Gauthron, Mountain View, CA (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.