The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jun. 18, 2008
Chung-hsing Wang, Hsinchu County, TW;
Chih Sheng Tsai, Taichung County, TW;
Ying-lin Liu, Hsinchu, TW;
Kai-yun Lin, Hsinchu, TW;
Chung-Hsing Wang, Hsinchu County, TW;
Chih Sheng Tsai, Taichung County, TW;
Ying-Lin Liu, Hsinchu, TW;
Kai-Yun Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.