The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jul. 27, 2007
Kevin J. Kerns, San Jose, CA (US);
Mayukh Bhattacharya, Fremont, CA (US);
Svetlana Rudnaya, San Jose, CA (US);
Kiran Gullapalli, Austin, TX (US);
Kevin J. Kerns, San Jose, CA (US);
Mayukh Bhattacharya, Fremont, CA (US);
Svetlana Rudnaya, San Jose, CA (US);
Kiran Gullapalli, Austin, TX (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.